Programmable delay line (PDL)
Delay lines are used within integrated circuits for a wide variety of applications, such as for adjusting or modifying the phase alignment between two signals. In complex digital systems, delay lines may be useful for such tasks as providing a phase delay to align the edges of a clock signal or providing a delay for a signal in order to synchronize it with another signal. Delay lines may be particularly useful in areas where multiple signals encountering differing propagation delays on their respective signal paths must be synchronized. Delay lines commonly provide a capacitor, a source of charging current for the capacitor, a reset switch, and a thresholding stage. An incoming pulse causes the reset switch to be opened, so that the capacitor begins to charge. The capacitor is charged up until its voltage is high enough to activate the thresholding stage. The output of the thresholding stage provides a digital signal which is propagated through to the output. After the reset switch closes, the delay line is ready for a new cycle. There are three types of variable delay lines including the semiconductor type which employs a semiconductor element, the fixed type which makes use of fixed taps from the signal line which is opposed to the ground line, and the sliding type which uses a sliding tap provided for the signal line which is opposed to the ground line. The semiconductor type delay lines include a programmable delay line semiconductor element and an output buffer semiconductor element mounted on a circuit board within a package such that the amount of delay is changed by a driving power or controller. Programmable delay lines are required for the generation of accurately shaped waveforms, and for delaying electronic signals. These waveforms are used in automated test systems (ATEs), to measure time intervals and to sample data at circuit interfaces. Specific applications require varying degrees of accuracy and resolution in the delay of the electronic signal. Programmable delay lines may be designed using random access memory (RAM), coupled oscillators, shift registers, charge coupled devices (CCDs), ramp comparators, multiplexed delay lines and tapped delay lines.
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