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Hpe_JTAG Boundary Scan Tool
Hpe_JTAG enables designers to debug their PCBs interactively (without the need to program a design into the PLDs), observe and debug their PLD designs, write scripts for all repetitive tasks and even setup automated tests, e.g. for limited lot productions. Hpe_JTAG supports the following JTAG instructions: • SAMPLE: The SAMPLE instruction is used to get a snapshot of the current pin states of a device in the JTAG chain. It does not influence the device operation. • EXTEST: The EXTEST instruction is used to check a connection between devices in one JTAG chain. The values of output pins can be set and the values of input pins can be read. In combination with the scripting interface EXTEST can be used to generate any testpattern. Examples for flash programming, SPI, I2C protocols etc. are preinstalled. • INTEST: If supported by the device, the INTEST instruction is used to check the internal functionality of a device in the JTAG chain. The values of input pins can be set and the values of output pins can be read. Hpe_JTAG provides a graphical user interface, but also powerful Python-scripting capabilities. Instead of graphically representing huge ball grid arrays with more than thousand IOs each, devices are represented by tabs. A filter function allows the user to display only signals that are currently of interest.
|Company name:||Gleichmann Electronics Research [ Homepage ]|
|Business address:||Softwarepark 37 4232 Hagenberg Austria|
|Telephone number:||+49 8165 999 5678|
|Fax number:||+49 8165 999 5678|
|Contact name:||Andreas Schwarztrauber [ Email ]|