Digital delay generator

Thursday, 01 February 2007

Digital delay generators, or programmable timing units, are electronic circuits used where it is desired to produce a number of signals at precise time intervals. For example, these devices are used for timing lasers, conducting electronics and materials research experiments, and other applications requiring very precise timing. As known, digital systems on integrated circuits require clocks for timing their functioning. A typical semiconductor device operates by being responsive to a plurality of digital control signals applied to its control signal input terminals. Timing generators provide control, clock and test signals for a plurality of applications in the fields of computer science and communications. Various systems have been used to generate a sequence of timing signals of variable signal-to-signal interval by programming digital counters to produce the timing signals at predetermined counts of a clock. Time delay simply refers to a signal not arriving when it is expected, whether it be a clock signal or a data signal. Hardware delays are often intentionally inserted into a complex circuit design to synchronize the arrival or evaluation of a particular signal in one part of the circuit with another part of the circuit, or to synchronize the arrival of two signals. The insertion of intentional delays is a critical aspect of circuit design. Digital delay generators are useful in a variety of electronic circuits, e.g., pulse generators, timing circuits, multiple-phase clock generators, high-speed logic testers and waveform generators. Circuits for generating programmable time delays have included tapped delay lines, high-speed counters and ramp comparators. Ramp comparators provide a flexible, low cost approach to generation of a wide range of precise time delays. In addition, they generally can be realized as monolithic integrated circuits.

Programmable time delays employing electronics generally fall into two categories, an RC analog technique employing a potentiometer or a digital technique which usually employs multiposition discrete switches. The RC technique, generally, relies upon the time interval created by the charging of a capacitor through a resistor. The digital technique relies upon a high frequency clock source which is frequency divided, and time is selected by digital switching. Generally, a digital delay generator receives as input samples of an input signal and provides the samples as an output after their respective delays. The digital delay generator receives as inputs: an incoming input signal the timing edges of which are to be delayed, and a digital data stream the numerical values of which define the magnitude of the delay for each period or timing edge of the input signal. The delay generator provides an output which is essentially the input signal with its periods or timing edges delayed in accordance with binary values encoded within the digital data stream. The data stream is typically organized into digital words comprising multiple bits so that a plurality of possible delay values can be encoded for each period or timing edge of the incoming waveform. Clock generation for digital systems generally requires clock frequencies that are stable, and in many cases the digital system clock frequencies are related by integer multiples. Typically, the master clock starts as the output of a crystal-controlled oscillator, then a digital version of the oscillator output is generated by various shaping circuits. These shaping circuits provide fast rise and fall times as well as symmetry between the two halves of the clock period. To generate clock signal symmetry, sometimes a higher frequency clock is divided down with a flip flop circuit to generate a clock with symmetrical half periods. The frequency of the clock generator is determined by using a specific pattern during the manufacturing process involved in the wafer production of the clock generator. An important competitive advantage can be obtained by providing a clock generator that can be configured late in the manufacturing process, preferably after wafer fabrication. Phase-locked-loop (PLL) based clock generators typically use read only memory (ROM) tables to store frequency selection and configuration information. This information can be altered by using a device specific mask during wafer fabrication. Many times, a phase lock loop (PLL) is used with a voltage-controlled oscillator (VCO) in a feedback loop to generate a high frequency clock from a lower frequency clock.

Programmable delay circuits have been extensively used in a variety of applications, mainly in the field of testing very large scale integrated circuits (VLSI). Digital delay generators are typically implementable in numerous circuit configurations and in numerous circuit technologies used for manufacturing integrated circuits, including complementary metal-oxide-semiconductor (CMOS), silicon bipolar and gallium arsenide. Test systems have been known to require the generation of accurate timing signals for use as stimulus for a device under test (DUT), oftentimes with delay increments ranging from a few picoseconds (ps) to several microseconds (us). Digital delay generators are particularly employed in instrumentation, automated test equipment and communications contexts. A typical automated test application involves the introduction of a variable delay to a timing edge which is then supplied to a circuit under test. The circuit can be observed to ascertain the effect of the delay on its operation. A typical communications application involves the transmission of data encoded in the phase modulation of a periodic waveform. The phase of the periodic waveform is varied as a direct function of the numerical value of a digital word comprising a digital data stream. A digital delay generator used to modulate the phase of a periodic waveform.

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