A typical phase-locked loop (PLL) circuit includes a phase frequency detector (PFD), a charge pump, a loop filter, and a voltage controlled oscillator (VCO) that produces a VCO signal. The charge pump circuit typically includes a transconductance cell, which may also be referred to as a transconductance amplifier, to generate current using input voltage signals, which are adjusted based on phase/frequency relationship between the reference clock and the VCO output signal. The phase detector circuit detects whether two signals are in or out of phase. One of these signals is a reference signal. The other one is generated in the PLL. There are generally two classes of phase detectors, analog and digital. With a digital phase detector, if the frequency difference between the input and VCO signals is too large, it is difficult for the PLL to achieve lock. Separate frequency detectors have been added to PLLs with digital phase detectors to ensure that the PLLs are able to achieve lock when the frequencies of the input and voltage controlled oscillator signals are far apart. The frequency detector of a phase-locked loop provides a frequency measurement of the VCO signal that is used to determine whether or not the frequency detector should assert control over the VCO signal. If the frequency detector is to assert control over the VCO signal, then the frequency detector is used to pull the frequency of the VCO signal close to a pre-established target frequency. Once the frequency of the VCO signal is within the capture range of the phase detector, control of the VCO is switched over to the phase detector. Voltage-controlled oscillators are commonly implemented using one or more integrated circuits (ICs) in topologies such as a ring oscillator topology. The ring oscillator topology provides a series of cascaded delay stages, where the output signal from the last delay stage is fed back to the input of the first delay stage. Total delay through the cascaded stages is designed to satisfy criteria for sustained oscillation. A voltage-controlled oscillator circuit (VCO) for constituting a phase-locked loop (PLL) circuit which produces a clock signal in synchronism with input data and also an input clock, corresponds to such an oscillator. An oscillating frequency of this VCO circuit is varied in response to a control voltage. The VCO produces the output signal of the PLL, and the various components of the PLL cooperate to cause the output signal to tend toward and eventually lock on to a desired output frequency and/or phase, which are based on a reference signal applied as an input to the PFD. For example, many PLL systems are configured to produce an output signal having the same frequency as the input signal, or having an output frequency which is a factor x/y of the input frequency. Passive loop filters for PLL circuit designs are popular due to their simplicity, but the control of their loop time constants lacks flexibility. Active loop filters used in conjunction with feed-forward charge pumps provide a wider range of loop time constants and often provide a decreased area of on-chip capacitance. The phase-frequency detector circuit provideS a raw control signal to a loop filter. The phase-frequency detector circuit provides the raw control signal in response to comparing the phase and frequency of the output clock signal to the reference clock signal. The loop filter often is a low-pass filter (LPF) that is arranged to provide a smoothed or averaged control signal in response to raw control signal. Typically, a voltage-controlled oscillator (VCO) is arranged to receive the control signal from the loop filter. In general, phase-locked loops can be classified, based on its method of implementation, into three main types: analog, mixed digital/analog, and all digital PLLs. A basic analog PLL consists of a phase detector and a low pass filter with a feed back loop closed by a local voltage-controlled oscillator (VCO). An all digital phase-locked loop (ADPLL) is a digital circuit with a digitally controlled oscillator (DCO) which can be periodically adjusted so that the DCO's output phase tracks the phase of a reference signal. A digital PLL generally produces output pulse stream or output clock pulses of which frequencies are related to a reference input frequency. A digital PLL requires a digital phase comparator which produces a direct current (DC) output in proportion to a phase difference between output clock pulses and reference clock input pulses. A phase-locked loop has a transfer function which depends on characteristic features of the analog components used for manufacturing such a loop. Such components are, for example, a voltage-controlled oscillator, capacitors, a current pump, a phase comparator. The transfer function may thus vary because of variations of parameters inherent in these various components, which is annoying for the performance of said loop. PLLs can be designed to operate in either a single-ended or differential fashion. As compared to a single-ended phase-locked loop (PLL), a differential PLL provides greater immunity to substrate noise, power supply or ground voltage fluctuations, and other undesirable effects.

Phase-locked loop (PLL) circuits are used for a variety of purposes, including signal demodulation, frequency synthesis, pulse synchronization of signals from mass storage devices, and regeneration of signals. A phase locked loop circuit operates by producing an oscillator frequency to match the frequency of an input signal. In the locked condition, any slight change in the input signal first appears as a change in phase between the input signal and the oscillator frequency. This phase shift acts as an error signal to change the frequency of the local PLL oscillator to match the change in the input signal. A phase-locked loop (PLL) compares the phase difference between a reference clock signal and a feedback clock signal and adjusts the frequency of the feedback clock signal to synchronize the clock signals. The frequency of the feedback clock signal locks to the frequency of the reference clock signal. Locking the output and input frequencies to be in phase is very critical in developing accurate and precise clocks that are used by digital signal processors (DSP) and for audio sampling frequencies and rates. A PLL circuit typically compares a variable-frequency signal to a reference signal to determine a frequency difference, which is then fed back to the variable-frequency signal generator to synchronize the two signals. Phase-locked loops which use feedback to maintain the frequency/phase of a signal in specific relationship with a reference signal are well known and commonly used in frequency synthesizers along with other applications. Frequency synthesizers are commonly used in radio receivers and transmitters to accurately generate a signal of any given frequency within a range of frequencies. Frequency synthesizers often use a phase-locked loop (PLL) to generate desired frequencies. A phase-locked loop circuit can be used to generate a stable high frequency output signal from a fixed low-frequency signal. The phase-locked loop circuit generates an output signal that is a multiple of the input signal by using a frequency divider in the feedback stage of the loop. The frequency divider divides the output signal from the oscillator before feeding the signal to the phase comparator. The dynamic performance of the frequency synthesizer that is used to generated clock signals is dependent on several parameters, including the natural frequency, the damping factor, the crossover frequency and the ratio of the comparison frequency to the crossover frequency. The first three parameters depend on the voltage controlled oscillator gain, the F/B divider value, the charge pump current, and the loop filter components. The ratio of the comparison frequency to the crossover frequency is dependent on the input divider (M) value, as well as the frequency of the input clock itself. The performance of the frequency synthesizer also depends on the performance of the charge pump located in the PLL. The charge pump pulse timing jitter and pulse amplitude noise both contribute to synthesizer phase noise. A typical charge pump includes circuitry to avoid what is known as the "dead zone," which occurs at or near the PLL "lock" state when the phase error is very small and the loop gain would otherwise approach zero. In many integrated circuits, the clock signals that drive an integrated circuit are generated by a PLL frequency synthesizer. Mobile communications transceivers generally comprise a single frequency synthesizer which serves as a local oscillator for both the transmit and receive sides of the transceiver. Such frequency synthesizers typically comprise one or more phase-locked loops (PLLs) that can be programmed to lock onto a specified frequency.