There are three primary configurable elements in a FPGA circuit: configurable logic blocks (CLBs), input/output (I/O) blocks, and programmable interconnects. Field programmable gate arrays consist of repeated blocks of logic called configurable logic blocks (CLBs), which can be programmed to perform as a specific combinational or sequential circuit. Each of these CLBs includes a block of configurable logic elements (CLEs) and corresponding programmable routing resources. The routing resources associated with the various configurable logic blocks can be programmed by the user to provide various connections among the configurable logic elements. In addition, the user can program the CLEs to implement different functions. The configurable logic blocks contain a variety of different logic functions, such as look-up tables (LUTs), registers, multiplexer (MUX) gates, programmable logic arrays (PLDs) programmable logic devices (PLDs), and the like. A lookup table (LUT) stores a truth table which implements that combinational logic function corresponding to the truth table. Each configurable logic block is associated with an adjacent portion of the interconnect structure. The programmable interconnect generally connects a single output of a CLB to an input of another CLB. An interconnect comprises metal wires and transistors that act as pass gates and signal buffers that preserve the signal integrity. Control of the interconnect transistors may be provided by an SRAM cell, a flash RAM cell, or external pins. The interconnect structure includes programmable interconnect points which control the connection of wiring segments in the programmable interconnect network of the FPGA. Each programmable interconnect point may be a pass transistor controlled by a configuration memory cell. Wire segments on each side of the pass transistor are either connected or not connected depending on whether the transistor is turned on by the corresponding configuration memory cell. FPGAs include other specialized blocks, such as block random access memories (BRAMs) and digital signal processors (DSPs). These specialized blocks perform more specific tasks than the CLBs, but can still be configured in accordance with a variety of options to enable flexible operation of the FPGA. FPGAs also include input/output blocks (IOBs), which contain circuitry that facilitates the transfer of signals to and from input/output (IO) pads of the FPGA. An IOB allows signals to be driven off-chip or optionally brought onto the FPGA onto interconnect segments. The IOB can typically perform other functions, such as tri-stating outputs and registering incoming or out-going signals. The I/O blocks provide the interface between the external pins of the IC package and the internal signals lines, including the programmable interconnects. In addition, field programmable gate arrays can also include other blocks, such as digital clock modules (DCMs), which contain circuitry required to manipulate clock signals. Most high-density field programmable gate arrays reside in systems that have a host processor, such as a microprocessor, microcontroller, digital signal processor, or any other suitable system controller having a bus interface.

FPGAs are constructed by forming standard layouts of semiconductor blocks on a substrate, but then allowing the interconnection of these blocks to be programmable as the need arises. A field programmable gate array circuit can be programmed to implement virtually any set of functions. Input signals are processed by the programmed circuit to produce the desired set of outputs. Such inputs flow from a user's system, through input buffers and through the circuit, and finally back out the user's system via output buffers which provide any or all of the following input/output (I/O) functions: voltage gain, current gain, level translation, delay, signal isolation or hysteresis. Almost all integrated circuits use input/output (I/O) buffers to connect internal circuit nodes to other circuits external to the integrated circuit. These I/O buffers can be input, output or bi-directional I/O buffers. Different types of FPGAs designed by various manufacturers also feature configurable I/O buffers. Output buffers can be configured as either a push-pull output or as an open drain output. Each I/O buffer may be designed to meet electrical specifications dictated by industry standards. Selection of the desired standard is done by configuration memory bits. Further, different power supplies are provided to the I/O buffer as needed by the standard. The programmable elements in an FPGA can be either one-time programmable or re-programmable. Re-programmable elements used in FPGA technologies may comprise transistors or other re-programmable elements as is well known to those of ordinary skill in the art. One-time programmable elements used in FPGA technologies may comprise antifuse devices. The programmed logic elements in the gate array are connected together by routing resources to form a desired integrated circuit. The routing resources are connected to each other and to the logic elements in the gate array by programmable elements. Programming of the logic blocks, the routing network and the input/output cells is selectively completed to make the necessary interconnections that establish one configuration thereof to provide the desired system operation/function for a particular application. With shrinking geometries in semiconductor technology, field programmable gate arrays are beginning to be embedded with functional circuit blocks in ASICs. Such blocks may include a processor, memory, and peripheral elements in a so-called system-on-chip (SOC), or multi-processor elements of a parallel computing integrated circuit. The main configurable portion of the FPGA, termed an FPGA core, is embedded in the ASIC to configurably interconnect the various functional circuit blocks of the ASIC or to form another functional circuit block of the integrated circuit.