|Electronic circuit design|
|Thursday, 18 January 2007|
Electronic circuit design and manufacturing are incredibly complex operations. A typical design flow for integrated circuit design includes many steps that proceed sequentially, with each step depending on the results of the previous steps. A semiconductor integrated circuit has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. A circuit design, which begins as a functional description of circuit logic, must be converted into circuit components, such as transistors, resistors, capacitors, and connecting wires, formed from areas of conductors, semiconductors, and insulators on a semiconductor silicon die. The design of integrated circuits is typically performed in three stages: logic design, logic synthesis, and physical design. The first stage is logic design, wherein the desired operation of the integrated circuit is defined. The second stage is logic synthesis, wherein the desired operation is translated into the required circuit elements for a given technology. Design engineers design an integrated circuit by transforming a circuit description of the integrated circuit into geometric descriptions of physical components that create the basic electronic components. The design of an integrated circuit transforms a circuit description into a geometric description called a layout. The process of converting specifications of an integrated circuit into a layout is called the physical design. The physical design assigns the placement of these elements and routing which creates the wire interconnect of these elements on the integrated circuit. Layout of the circuit devices involves the manual or automated layout of the circuit devices based on the sizes of the circuit devices determined by the circuit synthesizer during sizing of the circuit devices. Typically, a layout, or physical design, for an integrated circuit is generated from a schematic. A schematic defines the logical functions performed by the integrated circuit and how the functions are interconnected. The layout defines the physical components used to construct the functions defined in the schematic. This step involves generating a description of the design to be implemented in an appropriate machine-readable form. One of the commonly used methods for specifying a design is a hardware description language (HDL). HDLs, such as the very high-speed integrated circuit hardware description language (VHDL) or Verilog, are text-based approaches to digital logic design. VHDL and Verilog are allow definition of a hardware model at the gate level, the register transfer level (RTL) or the behavioral level using abstract data types. Hardware description languages permit hardware designers to define signals at a very high level of abstraction. This language contains specific functions and syntax to allow complex hardware structures to be described in a compact and efficient way. Hardware description language can be used to design a programmable logic device (PLD), such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD); a mask programmable device, such as a hardwired pin grid array (PGA), application-specific standard product (ASSP) or application specific integrated circuit (ASIC); a system formed from selected electronic hardware components; or any other electronic device.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. An EDA system is a computer software system designers use for designing integrated circuit (IC) devices. Electronic design automation applications assist engineers in designing integrated circuits. These applications provide sets of computer-based tools for creating, editing, and analyzing IC design layouts. These layouts are formed by geometric shapes that represent layers of different materials and devices on IC's. An integrated circuit designer uses a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. The netlist is used by a placement tool to place the selected cells at particular locations in an integrated circuit layout pattern. The interconnections between the cells are then routed along predetermined routing layers. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example. At a higher level of abstraction, a generic netlist is typically produced based on technology independent primitives. The generic netlist can be translated by the EDA system into a lower level technology-specific netlist based on a technology-specific library that has gate-specific models for timing and power estimation. The netlist is typically stored in computer readable media within the EDA system and processed and verified using many well known techniques. The netlist does not specify where on a circuit board or silicon chip the cells are placed or where the wires run which connect them together. Determining this geometric information is the function of a computer controlled placement process and a computer controlled routing process. Many integrated circuits are designed using computer-aided design (CAD) programs running on a workstation. The designer typically selects electronic components for the integrated circuit through a graphical user interface (GUI), which includes a graphical display screen and a computer mouse or similar pointing device. The CAD tool generates netlists including cells, logic gates and connections between them which perform the desired circuit behavior. The behavioral level hardware description language (HDL) netlist is typically the starting level for CAD tools because the HDL description file describes the behavior of the integrated circuit. The gate level HDL netlist is usually the level at which the functional verification of the integrated circuit is performed. The output of computer-aided design tool is a design database specifying the components of the design and how the components are interconnected. The components of a design may consist of large blocks that implement complex logic functions, memory blocks, logic gates, or other types of components. The design database is then passed as input to a layout tool, which typically includes a placement tool and a routing tool. Placement is the process whereby each component of the design is allocated to a physical position on the chip. Placement defines the location of the circuit elements on the integrated circuit. The aim of the placement tool is to place connected design objects in close physical proximity to one another. After placement is complete, a routing step is performed. Routing defines interconnections between circuit elements.
After placement and routing, it is often necessary to verify the behavior of the most critical signal paths at an earlier design stage in order to understand and identify possible problems and finding solutions thereof, which will be used at subsequent tuning steps to meet the design requirements and specification. This verification may be achieved by simulation and analysis. Simulation of a design is the execution of an algorithm that models the behavior of the actual design. Simulation dynamically verifies a design by monitoring behaviors of the design with respect to simulation test benches. Simulation provides the ability to analyze and verify a design without actually constructing the design and has many benefits in the design process. Two types of simulations may be used to verify the IC design: functional simulation and timing simulation. Computer-aided simulations and evaluations typically play a significant role in the development of a new integrated circuit design. Software based logic simulation and design tools presently are capable of performing functional and timing simulations for digital electronic designs which are written in a hardware description language. Logic design tools can specify circuit component placement as well as signal routing between placed components for a given circuit design. The abstracted signal representations can be translated to actual pins and circuitry on a microchip using any of a variety of commercially available fabrication and/or design tools. A cell-level simulator is used to gauge performance of individual logic cells made available by a given integrated circuit manufacturer. Typically, this type of simulator characterizes the behavior of the individual cells; more sophisticated combinational logic devices like multiplexors, counters, decoders, and encoders; and sequential logic devices like flip-flops and registers. Various timing analysis tools, including for both static and dynamic timing analysis, have been developed for use in designing integrated circuits. Static signal integrity analysis is typically used during the design verification stages of an electronic circuit to ensure the functionality of the silicon comprising the circuit for various electrical noise conditions. A noise problem in the design verification state of the electronic circuit may cause functional errors or may impact the frequency performance of the electronic circuit. If post-layout verification is successful, the design process is complete and the design is implemented in the target technology. To ensure proper operation and high-quality of electronic circuits, manufacturing tests must be run on fabricated devices to detect structural faults and eliminate defective parts or devices. Test patterns for a manufacturing test of an IC design are typically generated using an automatic test pattern generation (ATPG) tool.